中圖分類號：TN402 文獻標志碼：A DOI: 10.16157/j.issn.0258-7998.239803 中文引用格式： 李嘉欣，黃亞平，胡劼，等. 一種基于Quantus-reduce加速模擬仿真驗證分析的解決方案[J]. 電子技術應用，2023，49(8)：42-46. 英文引用格式： Li Jiaxin，Huang Yaping，Hu Jie，et al. A solution to accelerate simulation verification and analysis based on Quantus-reduce[J]. Application of Electronic Technique，2023，49(8)：42-46.
A solution to accelerate simulation verification and analysis based on Quantus-reduce
Li Jiaxin1，2，3，Huang Yaping1，2，3，Hu Jie1，2，3，Ling Qiuchan4，Yang Xiaochen4
(1.Sanechips Technology Co.，Ltd.， Shenzhen 518055， China； 2.National Key Laboratory of Radio Frequency Heterogeneous Integration，Shenzhen 518060， China； 3.State Key Laboratory of Mobile Network and Mobile Multimedia Technology，Shenzhen 518055， China； 4.Cadence Design Systems， Inc.， Shanghai 200120， China)
Abstract： With the continuous development of semiconductor technology, the scale of chip design is increasing. That makes much more complicated parasitic need to be considered in designs and also makes post-simulation cost much more loading. This article will discuss how to use Cadence's parasitic extraction tool Quantus for post-layout parasitic extraction, and use Quantus' Standalone Reduction(Qreduce) function to simplify the post-imitation netlist to reduce the size of the netlist and increase the speed of simulation. Cadence's Qreduce function is to perform equivalent operations on the RC network through mathematical operations to reduce the number of nodes, thereby reducing the size of the netlist, but at the same time ensuring that the accuracy will not cause a relatively large loss. This article will discuss the degree of post-simulation netlist reduction, the impact of simulation accuracy, simulation speed and memory consumption, and give key comparison indicators.
Key words : Qreduce；post-simulation netlist；simulation accuracy；simulation speed
